//===- SPIRVBasicBlock.cpp - SPIR-V Basic Block -----------------*- C++ -*-===//
//
//                     The LLVM/SPIRV Translator
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
// Copyright (c) 2014 Advanced Micro Devices, Inc. All rights reserved.
//
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// copy of this software and associated documentation files (the "Software"),
// to deal with the Software without restriction, including without limitation
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// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
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//
//===----------------------------------------------------------------------===//
/// \file
///
/// This file implements SPIRV basic block.
///
//===----------------------------------------------------------------------===//

#include "SPIRVBasicBlock.h"
#include "SPIRVEntry.h"
#include "SPIRVFunction.h"
#include "SPIRVInstruction.h"
#include "SPIRVStream.h"
#include "SPIRVValue.h"

#include <iostream>

using namespace SPIRV;

SPIRVBasicBlock::SPIRVBasicBlock(SPIRVId TheId, SPIRVFunction *Func)
    : SPIRVValue(Func->getModule(), 2, OpLabel, TheId), ParentF(Func) {
  setAttr();
  validate();
}

SPIRVDecoder SPIRVBasicBlock::getDecoder(std::istream &IS) {
  return SPIRVDecoder(IS, *this);
}

/// Assume I contains valid Id.
SPIRVInstruction *
SPIRVBasicBlock::addInstruction(SPIRVInstruction *I,
                                const SPIRVInstruction *InsertBefore) {
  assert(I && "Invalid instruction");
  Module->add(I);
  I->setParent(this);
  if (InsertBefore) {
    auto Pos = find(InsertBefore);
    // If insertion of a new instruction before the one passed to the function
    // is illegal, insertion before the returned instruction is guaranteed
    // to retain correct instruction order in a block
    if (Pos != InstVec.begin() && (isa<OpLoopMerge>(*std::prev(Pos)) ||
                                   isa<OpLoopControlINTEL>(*std::prev(Pos))))
      --Pos;
    InstVec.insert(Pos, I);
  } else
    InstVec.push_back(I);
  return I;
}

void SPIRVBasicBlock::encodeChildren(spv_ostream &O) const {
  O << SPIRVNL();
  for (size_t I = 0, E = InstVec.size(); I != E; ++I)
    O << *InstVec[I];
}

_SPIRV_IMP_ENCDEC1(SPIRVBasicBlock, Id)

SPIRVInstruction *SPIRVBasicBlock::getVariableInsertionPoint() const {
  auto IP =
      std::find_if(InstVec.begin(), InstVec.end(), [](SPIRVInstruction *Inst) {
        return !(isa<OpVariable>(Inst) || isa<OpLine>(Inst) ||
                 isa<OpNoLine>(Inst) ||
                 // Note: OpVariable and OpPhi instructions do not belong to the
                 // same block in a valid SPIR-V module.
                 isa<OpPhi>(Inst) || isa<OpUntypedVariableKHR>(Inst));
      });
  if (IP == InstVec.end())
    return nullptr;
  return *IP;
}

void SPIRVBasicBlock::setScope(SPIRVEntry *Scope) {
  assert(Scope && Scope->getOpCode() == OpFunction && "Invalid scope");
  setParent(static_cast<SPIRVFunction *>(Scope));
}
